![]() ![]() Liang and Hsiao propose to disable the PLL loop after acquiring the frequency lock to prevent the conflict in the normal operation while minimising the overhead. However, high-resolution timing circuit, which is used for adjusting the injection timing, increases the hardware overhead. Injection timing adjusting technique has been proposed to mitigate the conflict issue, as shown in Fig. Owing to the delay mismatch between the PLL feedback path and the injection path, a reference spur occurs because two different phases are driven by each path . However, injecting the reference clock to a VCO operating in a PLL loop causes a conflict issue, because there are two kinds of phase-aligning forces from the PLL and from the injection. Most of the state-of-the-art works put the ILO into a PLL, rather than letting it free-run . ![]() There have been some approaches for the frequency acquisition. First, a frequency acquisition is required due to the limited lock range of an ILO. ![]() However, there are a few critical design challenges to overcome. Recently, an injection-locked clock generator (ILCG), based on an injection-locked oscillator (ILO), has been widely studied because of its superior phase noise suppression .
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. Archives
January 2023
Categories |